- University of Michigan
EECS 578 - Correct Operation for Processors
and Embedded Systems
Prof. Valeria Bertacco
FALL 2015
Bibliography for paper presentations
Reliability
D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. Das.
Exploring fault-tolerant network-on-chip architectures.
In
Proc. Dependable Systems and Networks
, June 2006.
C. Iordanou, V. Soteriou, and K. Aisopos.
Hermes: architecting a top-performing fault-tolerant routing algorithm for networks-on-chips.
In
Proc. International Conference on Computer Design
, October, 2014.
S. Nomura, M. Sinclair, C.-H. Ho, V. Govindaraju, M. Kruijf and K. Sankaralingam.
Sampling + DMR: practical and low-overhead permanent fault detection.
In
Proc. International Symposium on Computer Architecture
, June 2011.
A. Meixner, M. Bauer, and D. Sorin.
Argus: low-cost, comprehensive error detection in simple cores.
In
Proc. International Symposium on Microarchitecture
, December 2007.
M. Powell, A. Biswas, S. Gupta, and S. Mukherjee.
Architectural core salvaging in a multi-core processor for hard-error tolerance.
In
Proc. International Symposium on Computer Architecture
, June 2009.
K. Aisopos, and L.-S. Peh.
A systematic methodology to develop resilient cache coherence protocols.
In
Proc. Symposium on Microarchitecture
, December, 2011.
Pre-silicon validation
H. Foster.
Trends in functional verification: a 2014 industry study.
In
Proc. Design Automation Conference
, June 2015.
N. Foutris, D. Gizopoulos, M. Psarakis, X. Vera, and A. González.
Accelerating microprocessor silicon validation by exposing ISA diversity.
In
Proc. Symposium on Microarchitecture
, December 2011.
J. Marques-Silva and K. Sakallah.
GRASP: a search algorithm for propositional satisfiability.
IEEE Transactions on Computers
, May 1999.
Post-silicon validation
A. Adir, M. Golubev, S. Landa, A. Nahir, G. Shurek, V. Sokhin, and A. Ziv.
Threadmill: a post-silicon exerciser for multi-threaded processors.
In
Proc. Design Automation Conference
, June 2011.
T. Hong, Y. Li, Sung-Boem Park, et al.
QED: quick error detection tests for effective post-silicon validation.
In
Proc. International Test Conference
, November 2010.
K. Cong, F. Xie, and L. Lei.
Automatic concolic test generation with virtual prototypes for post-silicon validation.
In
Proc. International Conference on Computer-Aided Design
, November 2013.
Runtime validation
K. Chen, S. Malik, and P. Patra.
Runtime validation of memory ordering using constraint graph checking.
In
Proc. International Symposium on High Performance Computer Architecture
, February 2008.
M. Dehbashi and G. Fey.
Transaction-based online debug for NoC-based multiprocessor SoCs.
Microprocessors and Microsystems
, May 2015.
Memory consistency validation
D. Lustig, C. Trippel, M. Pellauer, and M. Martonosi.
ArMOR: defending against consistency model mismatches in heterogeneous architectures.
In
Proc. International Symposium on Computer Architecture
, June 2015.
M. Zhang, J. Bingham, J. Erickson, and D. Sorin.
PVCoherence: designing flat coherence protocols for scalable verification.
In
Proc. International Symposium on High Performance Computer Architecture
, February 2014
Security
H. Kannan, M. Dalton, and C. Kozyrakis.
Decoupling dynamic information flow tracking with a dedicated coprocessor.
In
Proc. Dependable Systems and Networks
, June 2009.
A. Rane, C. Lin, and M. Tiwari.
Raccoon: closing digital side-channels through obfuscated execution.
In
Proc. USENIX Security Symposium
, August 2015.
P. Subramanyan, S. Ray, and S. Malik.
Evaluating the security of logic encryption algorithms.
In
Proc. International Symposium on Hardware-Oriented Security and Trust
, May 2015.
B. Cakir and S. Malik.
Hardware trojan detection for gate-level ICs using signal correlation based clustering.
In
Proc. Design, Automation and Test in Europe
, March 2015.
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