EECS 579: Digital System Testing (Fall 2001)
- Instructor: Professor John P. Hayes
- Class Schedule: Tuesday and Thursday 9:00 - 10:30 am
- Classroom location: EWRE Building, Room 153. The EWRE Building is just north
of the EECS Building, hidden between EECS and the G.G. Brown Lab. If you
don't know how to get to EWRE 153, click on these directions.
- Instructor's Office Hours: Thursday 10:30am-12:00pm and Friday 3:00-4:00pm.
- Other times by appointment. Please use e-mail for routine questions.
- Office location: EECS Building, Room 2114e, Tel. 763-0386
- Prerequisites: EECS 270 or equivalent course in digital logic design or
instructor's permission.
Note that EECS 478 is no longer a prerequisite for this course.
- Course Summary:
This course examines in depth the theory and practice of fault analysis,
test generation, and design for testability for
integrated circuits and systems. The topics to be covered include:
circuit and system modeling; fault sources and types; the single stuck-line
fault model; fault simulation methods; test generation algorithms for
combinational and sequential circuits, including PODEM; testability
measures; design-for-testability techniques; scan design; test compression
methods; logic-level diagnosis; self-checking circuits; built-in
self-testing (BIST); system-level diagnosis; processor and memory testing;
VLSI and system-on-a-chip (SOC) testing; design verification and its
relation to physical fault testing. A term paper or experimental/research
project will be part of the course. Current research issues, including
topics suitable for M.S. or Ph.D. thesis research, will be discussed.
The course should be of interest to undergraduate or graduate students
majoring in EE, CE or CSE (hardware or VLSI). Current research issues,
including topics suitable for M.S. or Ph.D. thesis research, will be
discussed.
- Texts:
- (New this term) Essentials of Electronic Testing by M. Bushnell & V. Agrawal,
Kluwer Academic Publishers, Boston, 2000. (Required text)
- Additional reference material will be placed on reserve in the Media Union
(Engineering) Library.
- Coursework:
Semester grades will be based on the following:
- Midterm exam (Tuesday October 30)
- Homework assignments (approximately six sets)
- Term project
- Honor Code:
This class will be conducted in accordance with the College of
Engineering's Honor Code. Read it if you are not familiar with
this traditional UM code of conduct.
Homework/Notes etc.
Miscellaneous
Reserve Book List: These books are on 2-hour
reserve for EECS 579 in the Media Union Library.
Term project handout. Posted October 9.
November Schedule: Prof. Hayes will be out of town. Nov. 8-9, 12-13 and 26-28.
During these periods
various guest lectures will be presented, as listed in the "Lecture Notes"
section below. Note that class on Nov. 8 will include a visit to the EECS
VLSI Testing Lab and an equipment demonstration.
Project Orals: Projects presentations will be scheduled on the follow
ing days:
Tuesday Dec. 11 in 153 EWRE (our usual classroom) 9:10-10:30am: Balasubramanian, Chen/Kang, Mishra, Senger.
Thursday Dec. 13 in 1301 EECS (Note the location and revised times) 8:00am-noon: Bezak, Burke, Cheng, Chueh, Hu,
Jayaram/K.Kim, Kao, N.Kim, Kumar, Liu, Rao, Yu. Lunch will be provided.
Homeworks and Solutions
Homework Assignment 1: Out Thursday Sept. 13. Due
Thursday Sept. 20.
Homework 1 Solutions: Posted Tuesday Sept. 25.
Homework Assignment 2: Out Thursday Sept. 27. Due
Thursday Oct. 4.
Homework 2 Solutions: Posted Thursday Oct. 11.
Homework Assignment 3: Out Thursday Oct. 11. Due
Thursday Oct. 18.
Homework 3 Solutions: Posted Wednesday Oct. 24.
Homework Assignment 4: Out Tuesday Nov. 6. Due
Thursday Nov. 15.
Homework 4 Solutions: Posted Thursday Nov. 22.
Homework Assignment 5: Out Sunday Nov. 25. Due Tuesday Dec. 4.
Homework 5 Solutions: Posted Dec. 10.
Exams and Solutions:
Practice Midterm Exam This is an old EECS 579 Midterm Exam.
Its solutions will be discussed in class on Thursday October 25. Note that the Midterm Exam
will be held on Tuesday October 30.
Solutions to Fall 2001 Midterm Exam. Posted Nov. 6, 2001.
Lecture Notes
These notes include copies of the instructor's transparencies in pdf format.
They will generally be placed on the web shortly before they are used in class.
The notes do not necessarily contain all the material covered in class.
Some papers of interest will also be added from time to time.
Lecture 01: (Sept. 06) Course Introduction.
Paper 01: B.T.Murray and J.P.Hayes,
"Testing ICs: getting to the core of the problem," IEEE Computer,
vol. 29, no. 11, pp.32-38, Nov. 1996.
Lecture 02: (Sept. 11) Intro. (contd). Faults.
Lecture 03: (Sept. 13) Testing Basics 1.
Lecture 04: (Sept. 18) Testing Basics 2.
Lecture 05: (Sept. 20) Testing Basics 3.
Lecture 06: (Sept. 25) Multiple Faults.
Lecture 07: (Sept. 27) Test Generation 1.
Lecture 08: (Oct. 02) Test Generation 2.
Lecture 09: (Oct. 04) Test Generation 3.
Lecture 10: (Oct. 09) Test Generation 4.
Lecture 11: (Oct. 11) Sequential Testing 1.
Lecture 12 (no new notes): (Oct. 16) Sequential Testing 2.
Lecture 13: (Oct. 18) Sequential Testing 3.
Lecture 14: (Oct. 23) Microprocessor Testing.
Lecture 15: (Oct. 25) Memory Testing.
Midterm Exam Review.
Lecture 16: (Nov. 01) Design for Test 1.
Lecture 17: (Nov. 06) Design for Test 2.
Lecture 18: (Nov. 08) VLSI Tester and Lab Demo. (Guest lecturer: Jay Sivagnaname)
Lecture 19: (Nov. 13) Delay Fault Testing.
(Guest lecturer: Joonhwan Yi)
Lecture 20: (Nov. 15) BIST 1.
Lecture 21: (Nov. 20) BIST 2.
Paper 02: E. Boehl, Th. Lindenkreutz, and R. Stephan:
"The fail-stop controller AE11," Proc. Intl. Test Conf., pp. 567-577, 1997.
Lecture 22: (Nov. 27) BIST 3. (Guest lecturer: Naga Kandasamy)
Lecture 23: (Nov. 29) Simulation. Paper 03: H. K. Kim and J.P. Hayes:
"Realization-independent ATPG for designs
with unimplemented blocks," IEEE Trans. on CAD, pp. 290-306, Feb. 2001.
Lecture 24: (Dec. 04) SOC Testing.
Lecture 25: (Dec. 06) Design Verification. /br>
