Behavioral Verification

  • Create .f files that include all your simulation options. Verilog-XL will use each line as a command line parameter. Then execute the file with "verilog_sst -f <file>.f". Example:


    • // CMOS7 Libraries
    -v /proj/ms8/lite7b_core_04/combined/verilog/unit_delay_models.v
    // Sequential primitives
    -v /proj/ms8/lite7b_core_04/combined/verilog/udps.v
    // IO Libraries
    -v /designPackages/cmos7_3v/R3.0/generic7_35_M4_r6/combined/verilog/GENERIC7_35_M4.v

    // TESTER MODULE
    /proj/ms8/verification/top/test_final_chip_noserial.v

    // All the include files (DEFINE statements)
    /proj/ms8/newblk/ms8_includes/ms8_include.v

    // Soft Instances
    /proj/ms8/newblk/ms8_includes/ms8_soft_instance.v

    // Weak pull device
    /proj/ms8/newblk/ms8_weak0_b0/netlists/ms8_weak0_b0.v
    /proj/ms8/newblk/ms8_strong1_b0/netlists/ms8_strong1_b0.v

    // The modules
    // Boot ROM
    /proj/ms8/newblk/ms8_bootrom_b0/netlists/ms8_rom_mem_b0.v
    /proj/ms8/newblk/ms8_bootrom_b0/netlists/ms8_bootrom_b0.v
    /proj/ms8/newblk/ms8_bootrom_b0/netlists/ms8_rom_ctl_b0.v
    /proj/ms8/newblk/ms8_bootrom_b0/netlists/ro512x8b1m8mgl7_qq00.v

    // Core
    /proj/ms8/newblk/ms8_core_b0/netlists/ms8_core_b0.v
    /proj/ms8/newblk/ms8_core_b0/netlists/ms8_ex_alu_b0.v
    <SNIP>
     
     

  • Create a top tester hierarchy level that verifies results automatically. This allows you to run an entire test bench quickly by not examining the waveforms.

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  • Speeding up simulations:


    • 1) Don't include entire hierarchy. This example keeps only signals in the core and not the memories and peripherals of this system. You can specify any subset of your hierarchy like this.
               // Set up SignalScan
               initial begin
                  $recordfile(`SST_FILE);
                  $recordvars(xms8_b0.xms8_chip_b0.xms8_core_b0);
               end

    2) Use VCS. VCS compiles your Verilog simulation into an executable. It's located in /usr/caen/cadence9404/vcs3.1.3

     3) Avoid clock periods with few common divisors. This will result in more simulation event queues and take more memory to execute. As an example, if you use two clocks with periods 100 and 101 this will take much longer to simulate than two clocks with periods 100 and 125.
     

  • Make specific tests to cover extreme cases. (e..g. memory bounds, every opcode, interrupts, etc.)

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  • Use a pseudorandom test generator to increase your testing coverage.