Design for Testability

Scan Chain Insertion

Synopsys Test Compiler can automatically create a scan chain for you. You can specify the number of scan chains
and even the order of the sequential elements in the scan chain. Synopsys can use scannable standard cells if your
library has them or it can insert muxes for scanning.

/* create scan test clock */
test_capture_clock_skew = clk_uncertainty*clock_period
create_test_clock gclk_c -waveform {0 20}
/* specify deticated scan signals */
set_scan_signal test_scan_enable -port test_se
set_scan_signal test_scan_in     -port test_si
set_scan_signal test_scan_out    -port test_so
set_test_hold   1                      test_scan
/* configure scan insertion */
set_scan_configuration -style multiplexed_flip_flop
set_scan_configuration -methodology full_scan
set_scan_configuration -chain_count 1
set_scan_configuration -clock_mixing mix_clocks
/* do the scan insertion */
preview_scan
insert_scan -map_effort high
check_test
/* create reports */
report_test -coverage               > scan_test.coverage
report_test -faults -class untested > scan_test.untested

insert_scan will map the sequential cells to scannable ones and also do any optimizations to maintain timing constraints.
However, insert_scan doesn't always do the best job at this. You can make your initial compile use scannable cells so
that they are considered in your timing. This is done with the -scan option. Then use insert_scan -map_effort_high to
create the scan connections.

Controlability

insert_scan is supposed to add logic to disable tri-state drivers. This prevents bus contention during testing. However,
insert_scan sometimes doesn't do this. You can manually add a control signal in your design to do this. This is also a good
idea to self-stimulate peripherals during test mode. Simple connect input busses to output busses with a mux and it will
improve your fault coverage.

Test Coverage

Once the scan chain is created and it has a clean check_test, you can generate fault coverage vectors.