Timing Verification

It is a good idea to do both static and dynamic timing analysis. Static timing analysis
checks the longest/shortest paths in a given circuit under all possible input combinations.
Dynamic timing analysis uses only the simulated input combinations. It is easy to see
that static timing is really a superset of dynamic timing analysis and is, therefore, preferred.
However, to make sure there are no discrepencies, most people do static AND dynamic
timing verification.

After synthesis - Static timing in Synopsys

After asserting your design constraints (clocks, input/output delay, output load), generate
timing reports:

    report_constraints -all_violators -verbose > report.constraints
    report_timing -path end -delay max -max_paths 200 -nworst 2 > report.paths
    report_timing -path full -delay max -max_paths 5 -nworst 2 > report.full_paths
    report_area > report.area

Confirm that the constraints are correct in the report.constraints file. Then you can examine
the timing reports for the results. A typical timing report looks like this:

****************************************
Report : timing
        -path end
        -delay max
        -nworst 2
        -max_paths 200
Design : ms8_core_b0
Version: 1998.02-1
Date   : Thu Jun 24 11:44:42 1999
****************************************

Operating Conditions: TYP Library: lite7b_core_04
Wire Loading Model Mode: top

Design Wire Loading Model Library
------------------------------------------------
ms8_core_b0 10000_CELLS lite7b_core_04

Endpoint                         Path Delay     Path Required     Slack
------------------------------------------------------------------------
swi_req (inout)                     9.82 f            3.65        -6.17
swi_req (inout)                     9.82 r            3.65        -6.17
ex_mem_addr_b[14] (out)            10.92 f            4.75        -6.17
<SNIP>

For more detail, examine the full paths. From the full path, you will be able to determine whether
the violation is a false path, a buffering problem, the constraint is to strict, etc.

After synthesis - Dynamic timing

Output an SDF file from Synopsys using:

write_timing -output "myoutput.sdf" -load_delay cell -format sdf -context verilog

This creates a file with all delays (net and cell) lumped into each cell. Also output the
gate level Verilog model:

write -hierarchy -format verilog -output "verilog_netlist_file.gate.v"

Then you can use the $sdf_annotate command to include the lumped delays in your
Verilog simulation:

$sdf_annotate("myoutput.sdf", xms8_b0,,"/tmp/myoutput.sdflog");

Any timing violations will be output to standard output and also put in the SDF log
file to exaamine later.

After P&R

Use the extracted information from the P&R tool. You can use PrimeTime to do the
timing verification, the physical design tool, or both.
More coming soon...