Course Schedule for EECS627 - VLSI Design II

Date (week)	Exams / Project / Lab Dates	Recitation Topics	Suggested Project Progress
January 9     (1)		Lab 1 handout (in lecture)	Form project teams
January 11			start project topic research
January 13		Lab 1 discussion Lab 2 handout
January 16   (2)	NO CLASS - MLK - extra office hrs
January 18	Project Proposal Due -  proposal review mtgs
January 20	Lab 1 due	Lab 2 discussion, Lab 3 handout
January 23   (3)
January 25			Algorithmic Simulation
January 27	Lab 2 due	Lab 3 discussion
January 30   (4)			Verification Environment
February 1
February 3	Lab 3 due	Memory Design, compilers
February 6 (5)	NO CLASS		Floorplan/Partitioning
February 8
February 10		Primetime
February 13 (6)			Behavioral Model coded
February 15	Design Review 1
February 17		Clock generation
February 20 (7)			Behavioral Model debugged
February 22	MIDTERM
February 24		Design for test	Partitioning for design automation
February 27 (8)	Spring Break - no class		Detailed Floorplan
March 1	Spring Break - no class		RTL, synthesis, place, route, annotate
March 3	Spring Break - no class		1 module done, design flow debugged
March 6     (9)
March 8
March 10		IO Pads	RTL, syn, P&R, annotation :  10%
March 13 (10)
March 15	NO CLASS
March 17		Q & A	RTL, syn, P&R, annotation :  30%
March 20  (11)
March 22
March 24	Design Review 2	Q & A	RTL, syn, P&R, annotation :  100%
March 27  (12)
March 29
March 31		Q & A	Global Design: Power, Clock, Routing
April 3  (13)
April 5
April 7		Q & A	Timing Closure : Iterate through flow
April 10 (14)
April 12
April 14		Q & A	Layout Verification
April 17 (15)	FINAL EXAM
April 25	Final Presentations		Tape Out

Milestones in Bold are due dates for lab assignments and project reviews/proposals, milestones in italics are suggested project milestones to help keep the projects on track.