Project Ideas  - EECS 627

Projects can be combined to make more comprehensive designs. Preferred team size is 3 - 4 students.  Smaller or larger team sizes are allowed based on project size in discussion with the instructor. Project teams will start to organize themselves during the first class and all teams should be formed by the end of the first week of classes.

IP-Blocks:

- Encryption chip for the Advanced Encryption Standard  (Rijndael algorithm) with self-test upon power-up

- Public key encryption using Montgomery or Galois Field multiplier

- IP Packet Forwarding Engine (with possibly with Encryption / Decryption)

- Ethernet Controller for packet transmission/reception and encapsulation / de capsulation

- Viterbi  decoder  / Turbo coders as part of a wireless backend.

- Game or graphics coprocessor for rendering acceleration

- Arithmetic co-processor implementing complex numerical algorithms

- MPEG compression / decompression with motion detection

-  JPEG encoder / decoder combined with low power techniques.

- DSP cores  and VLIW architectures

- mulit-core processor design with shared cache.

- Baseband processor architecture for CDMA / TDMA  / GSM baseband processing.

- Application specific processors with ISAs specifically designed for efficient execution of compression or encryption algorithms or other applications.

- Based band digital signal processing, such as JPS or Bluetooth



Analog:  

- PLL / DLL design that is incorporated in a larger design.

- Switch Cap  / DAC / ADC

- VCO

- Low voltage analog design


Custom Design / Technology Studies:

- Low power cache design (with dynamic or static Vt / Vdd scaling)

- Multi-Vdd Microcontroller design with voltage converters

- Dual-Vt / DTCMOS Microcontroller design for high performance / low leakage power

- Subthreshold mulit-core processor design.

- Soft-Error tolerant design and reliable design

- On-line checking and diagnosis

- Process variation tolerant design and test chip measurement structures.

- Microcontroler with process variation compensation using region based adaptive body biasing / Dual-Vt assignment and automatic tuning.

- Self tuning Microcontroller designs with dynamic voltage and frequency scaling using Razor type of tuning or canary cir circuits.

- Asynchronous micro controller datapath for ultra-high speed or low power.

- GALS (globally asynchronous / locally synchronous) SOC or processor design

- Adiabatic datapath design

- High speed arithmetic coprocessor or datapath  using advanced logic family such as LSDL logic or OPL logic

- New clocking schemes, such as rotary clocks, standing waves, resonating clocks.

- Design methodologies: Library design issues (large libraries vs. small etc.), new timing closure flows.

Something different:  

- Image sensor array with image processor

- MEMS

- FPGA / Reconfigurable computing