MICL Seminars

Upcoming Seminars

Friday  Apr. 18, 2014
A Whole New Ballgame - Preventing and Creating Surprise in Hardware Cyber at DARPA
Kerry Bernstein
Program Manager at DARPA Microsystems Technology Office
DARPA
2:00pm - 3:00pm in 1500 EECS

 
Past Seminars

Monday  Mar. 31, 2014
Making chips perfect – every time. The increasing need for mixed-signal design verification.
Scott Morrison
Senior Member of Technical Staff
Texas Instruments


Monday  Mar. 10, 2014
High-Performance and Low-Voltage Circuits for Tera-Scale Multi-core Microprocessors and SoCs
Himanshu Kaul
Research Scientist
Intel Circuits Research Lab


Monday  Nov. 25, 2013
Challenges of calibrated time-interleaved high-speed ADCs
Aaron Buchwald
Entropic Communications


Monday  Nov. 04, 2013
Power Delivery in Heterogeneous Nanoscale Integrated Circuits
Eby Friedman
Professor
University of Rochester


Monday  Oct. 28, 2013
Serial Link and Channel Co-Design for Low Power Signaling on a Multi-Chip Module
John Poulton
Senior Scientist
NVIDIA, Inc.


Monday  Oct. 21, 2013
Highly-Integrated CMOS Optical Transceivers
Tony Chan Carusone
Professor
University of Toronto


Monday  Sep. 30, 2013
A Whole New Ballgame - Preventing and Creating Surprise in Hardware Cyber at DARPA
Kerry Bernstein
Program Manager, Microsystems Technology Office
DARPA


Wednesday  Jul. 24, 2013
Medical Imaging: Technological Innovation that Can Improve Your Life
Michael Cole
Fellow and Design Manager for Precision Converters Analog Devices, Inc.
Analog Devices


Friday  May. 24, 2013
Neuromorphic Chip Design with a Scalable Architecture for Learning in Networks of Spiking Neurons
Jae-Sun Seo
Research Staff Member
IBM T.J. Watson Research Center


Thursday  Apr. 11, 2013
Successive Approximation and Time Interleaving for Sub-90nm CMOS ADCs
Rick Carley
Professor
Carnegie Mellon University


Monday  Apr. 08, 2013
Holistic Circuits: or How I Learned to Stop Worrying and Love the End of Moores Law
Ali Hajimiri
Director of Microelectronics Laboratory
California Institute of Technology


Monday  Mar. 25, 2013
Challenges in building resilient, energy-efficient processors and SoCs
Jim Tschanz
Intel Circuits Research Lab


Monday  Feb. 25, 2013
Efficient Neural Computing using Cellular Array of Magneto-Metallic Neurons
Dr. Kaushik Roy
Roscoe H. George Chair of Electrical & Computer Engineering
Purdue University


Monday  Feb. 11, 2013
Innovation at Texas Instruments – How You Can Shape the Future
Art George
Senior vice president and manager over Analog Engineering Operations
Texas Instruments


Friday  Feb. 01, 2013
Inside Intel Logic Technology Development: Taking SRAM From 32nm Planar to 22nm Tri-gate Technology
Dr. Eric Karl
Design Engineer
Intel Corporation

 

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