Electrical Engineering and Computer Science

ACAL Seminar

Run-time adaptive performance control and design issues in subthreshold SRAM

Masanori Hashimoto

Associate Professor
Osaka University
 
Friday, May 20, 2011
2:00pm - 3:30pm
Beyster Bldg. 3725

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About the Event

This talk consists of two parts; run-time adaptive performance control and design issues in subthreshold SRAM. First I will present run-time adaptive performance control with on-chip sensors that predict timing errors. The sensors embedded into functional circuits capture delay variations due to not only die-to-die process variation but also random process variation, environmental fluctuation and aging. By compensating circuit performance according to the sensor outputs, we can overcome PVT worst-case design and reduce power dissipation while satisfying circuit performance. We applied the adaptive speed control to subthreshold circuits that are very sensitive to random variation and environmental fluctuation. Measurement results of a 65nm test chip show that the adaptive speed control can compensate PVT variations and improve energy efficiency by up to 46% compared to the worst-case design and operation with guardbanding. Next, I will briefly explain two design issues in subthreshold SRAM. First, soft error rates from 0.3V to 1.0V in 65nm for neutron and alpha particles are introduced, and their trends are discussed. Then, a self-timed average-performance-oriented subthreshold processor for coping with large variation in SRAM read time is presented. Measurement results with a 65nm test chip show that the proposed self-timed operation reduces the execution time of SHA-1 by 82% at 0.4 V supply voltage, and saves energy by 40% to attain 1MHz operation, compared to the conventional synchronous operation with guardbanding,

Biography

Masanori Hashimoto received the B.E., M.E. and Ph.D. degrees in Communications and Computer Engineering from Kyoto University, Kyoto, Japan, in 1997, 1999, and 2001, respectively. Since 2004, he has been an Associate Professor in Department of Information Systems Engineering, Osaka University. His research interest includes timing and power integrity analysis, ultra low power design, and design for variability and reliability.

Additional Information

Contact: Edward Chusid

Phone: 764-4329

Email: ejc@eecs.umich.edu

Sponsor: EECS-CSE-ACAL

Open to: Public