About the Event
Reports from various organizations have identified multiple challenges on the road to Exascale computing. These challenges include the unrelenting issues of performance, scalability, and productivity in the face of ever-increasing complexity; they also include the relatively new priorities of energy-efficiency and resiliency. Not coincidentally, recently announced HPC architectures, such as RoadRunner, Tianhe-1A, Tsubame, Titan, Dash, and Sequoia, illustrate that emerging technologies, such as graphics processors, system-on-a-chip designs, and non-volatile memory can provide innovative solutions to address some of these challenges. Our early experiences on these systems have demonstrated performance and power benefits; however, we have also experienced major challenges in productivity, portability, and performance stability. Taken together, these issues are impeding the adoption of these innovative architectures by the broader community. In this presentation, I will present two approaches to addressing these challenges. First, GA-GPU is a Library-based global address space (GAS) programming model for scalable GPU computing systems, which simplifies the programming challenge by unifying data access and control of the system’s aggregate GPU memory. Second, the Hierarchical COOperation (HiCOO) architecture for scalable communication in GAS programming models creates a cooperative communication architecture that is scalable and more resilient than existing approaches.
Jeffrey Vetter is a Distinguished R&D Staff Member and Group Leader at Oak Ridge National Laboratory (ORNL), and a Joint Professor of Computer Science at the Georgia Institute of Technology (GT). In addition, Dr. Vetter is the Project Director for the NSF Track 2D Experimental Computing Facility, named Keeneland, for large scale heterogeneous computing using graphics processors, and the Director of the NVIDIA CUDA Center of Excellence. He earned his Ph.D. in Computer Science from the Georgia Institute of Technology, and, his research explores emerging architectures for HPC. More information is available at http://ft.ornl.gov/~vetter/.