About the Event
Analog to digital conversion techniques for nanometer CMOS are introduced. First, a 1.5GS/s 7b flash ADC is presented. We advance a comparator redundancy technique by employing random and deliberate mismatch to set the comparator thresholds and eliminate the need for a low-impedance high-precision resistor ladder. Unusually, the proposed technique exploits large random variation in comparator offset. This enables the use of low precision dynamic comparators that can be optimized for speed.
Second, a 9b 1GS/s 2-stage pipeline ADC is presented. This architecture achieves high performance with a low-gain op-amp and low accuracy comparators. A reduced MDAC gain relaxes the op-amp gain and bandwidth requirements and trades MDAC output swing for reduced op-amp power. This technique is assisted by a comparator redundancy scheme that decouples the 2nd stage sub-ADC performance from comparator matching requirements. A simple code-search algorithm calibrates the sub-ADCs and at the same time corrects any ADC errors from finite op-amp gain, offset and non-linearity. Digital trimming of a delay chain eliminates mismatch in the 1st stage sampling paths to provide a simple, low power alternative to a dedicated front-end S/H.
Third, a 9b 2GS/s two-times interleaved pipeline ADC is presented. This architecture leverages op-amp sharing and 2nd stage sub-ADC sharing between two time-interleaved MDACs to reduce power and area. Furthermore, this technique eliminates the need for correcting ADC errors due to gain and offset mismatch between channels.