University of Michigan
EECS Department
Electrical and
Computer Engineering
EECS Building
1301 Beal Avenue
Ann Arbor, MI 48109-2122
Defense Event
Analog Front-End Circuits For Massive Parallel 3-D Neural Microsystems
Khaled Mohamed Alashmouny
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Monday, January 14, 2013
3:00pm - 5:00pm 3316 EECS
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About the EventUnderstanding the brain dynamics has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels actually doubles every 7 years, which implies that a few thousands channels recording system should be available in the next two decades. This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystem. Three analog front-ends (AFE) have been developed to scale both power and area on both circuit and system levels. The circuits operate with a supply voltage down to 0.5 V and consume a minimum power of 1.4μW per channel.
The first analog front-end have optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. The second analog front-end provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computation power outside the brain. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes.
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Additional Information
Sponsor: Euisik Yoon
Open to: Public
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