Electrical Engineering and Computer Science

ACAL Seminar

Optimizations for Cache-Coherent Networks-on-Chip

Natalie Enright Jerger

Assistant Professor
University of Toronto
 
Tuesday, February 12, 2013
4:00pm - 5:30pm
1670 BBB

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About the Event

As transistors continue to scale according to Moore’s Law, efficient and scalable communication mechanisms will be required to realize the performance potential of many-core architectures. The increased demand for on-chip communication and the poor scaling of long global wires have made packet-switched networks-on-chip (NoC) a compelling choice for the communication backbone in these next-generation systems. Current NoC architectures are largely agnostic to the communication demands of the applications and the underlying architecture. In this talk, I will discuss research which explores increasing the functionality within the NoC to better match the demands of the coherence protocol. First, I will present a novel flow control technique that improves performance and buffer utilization in the face of short coherence control packets. Short control packets arise in NoCs due to abundant wiring resources. Second, I will present NoC support for routing collective communication. Collective communication, such as broadcast, multicast and reduction is often required by the coherence protocol. We propose light-weight multicast-reduction support that reduces network load which in turn improves overall performance. Our multicast-reduction support allows NoCs to better match the needs of current and emerging applications. These NoC optimizations for cache coherence protocols can provide low-latency, high bandwidth communication with low overhead.

Biography

Natalie Enright Jerger joined the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto as an Assistant Professor in 2009. Prior to joining the University of Toronto, she received her MSEE and PhD from the University of Wisconsin-Madison in 2004 and 2008 respectively. She received her Bachelor's degree from Purdue University in 2002. Her current research explores performance and power optimizations for sharing and communication patterns in on-chip networks and cache coherence protocols for many-core architectures. She is also interested in improving the programmability of many-core architectures. In 2009, she co-authored a book on On-Chip Networks with Li-Shiuan Peh. Her research is supported by NSERC, Intel, CFI, AMD and Qualcomm.

Additional Information

Contact: Lauri Johnson

Phone: 763-4921

Email: lkjohns@umich.edu

Sponsor: Reetu Das

Open to: Public