Defense Event

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge

Debapriya Chatterjee

Monday, April 22, 2013
1:00pm - 3:00pm
3725 BBB

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About the Event

Today, design verification is by far the most resource and time-consuming activity of any new digital integrated circuit development. Within this area, the vast majority of the verification effort in industry relies on simulation platforms, which can be implemented either in hardware or software. A "simulator" includes a model of each component of a design and has the capability of simulating its behavior under any input scenario provided by an engineer. Thus, simulators are deployed to evaluate the behavior of a design under as many input scenarios as possible and to identify and debug all incorrect functionality. Two features are critical in simulators for the validation effort to be effective: performance and checking/debugging capabilities. A wide range of simulator platforms are available today: on one end of the spectrum there are software-based simulators, providing a very rich software infrastructure for checking and debugging the design's functionality, but executing only at 1-10 simulation cycles per second (compare this to actual products, which execute at GHz speeds). On the other end of the spectrum, there are hardware-based platforms, such as accelerators, emulators and even prototype silicon chips, providing higher performances by 4 to 9 orders of magnitude, at the cost of very limited or non-existent checking/debugging capabilities. As a result, today, simulation-based validation is crippled: one can either have satisfactory performance on hardware-accelerated platforms or critical infrastructures for checking/debugging on software simulators, but not both. This dissertation solves precisely this problem: it brings together the two ends of the spectrum by presenting solutions that offer high-performance simulation with effective checking and debugging capabilities. Performance of software simulators can be boosted by exposing the parallelism inherent in the design model to the underlying execution substrate. To this end, this dissertation leverages inexpensive off-the-shelf graphics processors as massively parallel execution substrates. For hardware-based platforms, the dissertation provides solutions that offer enhanced checking and debugging capabilities by abstracting the relevant data to be logged during simulation so to minimize the cost of collection, transfer and processing. Altogether, the contribution of this dissertation has the potential to solve the challenge of digital design verification by enabling effective high-performance simulation-based validation.

Additional Information

Sponsor(s): Valeria Bertacco

Open to: Public