Defense Event

Architecture Independent Timing Speculation Techniques in VLSI Circuits

Matthew R. Fojtik

Tuesday, October 08, 2013
3:00pm - 5:00pm
Johnson Rooms B & C, Lurie Bldg.

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About the Event

Digital circuits must ensure correct operation despite delay variations, thus safety margins must be put in place which come at a power and performance cost. The Razor system proposed eliminating these timing margins by running a circuit with occasional timing errors and correcting the errors when they occur. Several existing Razor styles have been proposed, however none had been applied to a complete existing processor because of design complexities. This thesis introduces Razor using two-phase latches. By utilizing time borrowing as an error correction mechanism, it allows for Razor to be applied without the need to reload data or replay instructions. This allows for Razor to be blindly and automatically applied to existing designs. By demonstrating how to transform conventional flip-flop based designs, including those which use clock gating, to two-phase latch based timing, Razor can be automatically added to many existing processors. Two forms of latch based Razor are proposed. First, Bubble Razor involves rippling stall cycles throughout a circuit in response to timing errors and is applied to the ARM Cortex-M3 processor, the first Razor technique applied to a complete, existing processor. The second latch based Razor technique, Voltage Razor, uses voltage boosting to correct for timing errors.

Additional Information

Sponsor(s): Dennis Sylvester

Open to: Public