Defense Event

Circuit Techniques for Adaptive and Reliable High Performance Computing

Bharan Giridhar

 
Friday, December 13, 2013
2:00pm - 4:00pm
3725 Beyster Bldg.

 

About the Event

Increasing power density with process scaling has caused stagnation in the clock speed of modern microprocessors. Thus, designers have adopted multicore architectures in order to keep up with the rising demand for computing throughput. At the same time, applications are not entirely parallel, and improving single thread performance continues to remain critical. Reliability is also worsening with process scaling, and margining for failures due to process and environmental variations in modern technologies consumes an increasingly large portion of the power/performance envelope. With multicore computing, reliability of signal synchronization between cores is also becoming increasingly critical. This forces designers to search for alternate efficient methods to improve compute performance while addressing reliability. Accordingly, this talk presents circuit and architectural techniques for variation-tolerance, performance and reliability targeted at datapath logic, signal synchronization and memories. Firstly, Adaptive Robustness Tuning (ART) for domino logic is presented to provide ~71% performance gains over conventional domino logic in 65nm CMOS. Secondly, for synchronization, pulse-amplification based dynamic synchronizers are presented that improve MTBF by >106× over jamb latches and double flip-flops at 2GHz in 65nm CMOS. Thirdly, a reconfigurable sensing scheme for 6T SRAMs is presented that employs auto-zero calibration and pre-amplification to improve sensing reliability by up to 1.2σVth in 28nm CMOS – this increased reliability is traded for ~42% sensing speedup. Finally, a main memory design methodology based on 3D-stacked DRAMs is presented to address reliability and power in the context of Exascale computing.

Additional Information

Event Sponsor: David Blaauw

Open to: Limited