About the Event
This talk describes ultra-low voltage circuits, special-purpose accelerator and network-on-chip (NoC) technologies to enable higher energy efficiency and tera-scale compute performance with increasing core counts and transistor integration in microprocessors and SoCs. Ultra-low voltage operation can increase energy efficiency by almost an order of magnitude but poses a challenge for circuit designers. Floating-point computations are power and performance limiters for a range of applications, while on-chip communication eats into the computation power budget and also has to accommodate increasing design heterogeneity. The following technologies will be described to address these challenges – (i) circuit techniques to enable a wide supply voltage range of operation across different compute units and process technologies, (ii) A variable-precision floating-point unit with real-time certainty tracking enables low-precision computations while maintaining single-precision accuracy for up to 3.1X increase in energy efficiency even at nominal supply voltage, and (iii) A source-synchronous hybrid packet/circuit-switched NoC in 22nm Tri-gate CMOS enables up to 20Tb/s communication across a 256-node mesh with independent voltage/clock domain per router while increasing energy efficiency by removing intra-route data storage.
Himanshu Kaul received the Bachelor of Engineering degree in Electrical and Electronics engineering from the Birla Institute of Technology and Science, India, in 2000. He received his M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan, Ann Arbor, in 2002 and 2005, respectively. Since 2004, he has been with Intel Corporation's Circuits Research Lab, in Hillsboro, Oregon, where he is currently a research scientist. His research interests include low-voltage and high-performance circuit design and on-chip communication.