About the Event
Channel coding has become essential in state-of-the-art communication and storage systems for ensuring reliable transmission and storage of information. These systems have adopted channel codes such as LDPC and turbo codes to close the gap towards the Shannon limit. Their goal is to achieve high transmission reliability while keeping the transmit energy consumption low by taking advantage of the coding gain provided by these codes. Lower transmit energy is enabled at the cost of extra decode energy. Therefore the lowest total energy is achieved with a decoder that provides both good coding gain and high energy-efficiency. This thesis demonstrates the VLSI implementation of near-capacity channel decoders using the LDPC, nonbinary LDPC (NB-LDPC) and polar codes with an emphasis of reducing the decode energy.
LDPC code is a widely used channel code due to its excellent error correcting performance. However, memory dominates the power of high-throughput LDPC decoders. As a remedy, the memories used in the decoder are replaced with a novel non-refresh embedded DRAM (eDRAM) which takes advantage of the deterministic memory access pattern and short access window of the LDPC decoding algorithm to trade-off retention time for faster access speed. With architectural techniques employed to accommodate the eDRAM, the resulting LDPC decoder achieves state-of-the-art area- and energy-efficiency.
NB-LDPC code achieves even better error correcting performance than LDPC at the cost of significantly higher decoding complexity. However, the factor graph is simplified which permits a fully parallel architecture with low wiring overhead. To reduce the overall dynamic power of this large decoder, a fine-grained dynamic clock gating technique is applied based on a simple node level convergence. The techniques allows remarkable reduction in dynamic power allowing the decoder to achieve high energy-efficiency while achieving a high-throughput.
The recently invented polar code has a comparable error-correcting performance with LDPC at similar block lengths. However, the easy reconfigurability of code rate as well as block length makes it desirable in numerous applications where LDPC is not competitive. In addition, the regular structure and simple processing enables a highly efficient decoder in terms of area and power. Using the belief-propagation algorithm with architectural and memory improvements, a belief-propagation polar decoder is demonstrated achieving high throughput and high energy- and area-efficiency.
The demonstrated energy-efficient decoders have advanced the state-of-the-art. The decoders will allow the continued reduction of decode energy for the latest communication and storage applications. The new developed techniques are widely applicable to designing low-power DSP processors.