Defense Event

Nano-Scale Feature Profile Modeling of Plasma Material Processing

Chad M. Huard

Wednesday, May 23, 2018
1:00pm - 3:00pm
Johnson Rooms B & C, LEC

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About the Event

Abstract: For the last six decades the down-scaling of transistors in semiconductor devices, referred to as Moore’s Law, has driven improvements in processing performance, power efficiency and cost. For the last several years, continuing Moore’s Law has required innovative changes to process and device design. Challenges in plasma etching, particularly uniformity and selectivity, are becoming limiting factors in semiconductor manufacturing. To overcome these limitations, new processes are being developed, including atomic layer etching (ALE) – the etching analog of atomic layer deposition. In this thesis computational studies describing the physics behind continued scaling of plasma etching are discussed. A new computational model of plasma etching which accounts for the transport of ion energy and radical species through the polymer overlayer which forms during fluorocarbon plasma etching was developed. By separating neutral reactions from ion bombardment, ALE can reduce the dependence of etch rate on feature aspect ratio, a cause of micro-scale non-uniformity. Using self-limiting reactions, ALE can also significantly improve wafer-scale uniformity. High selectivity to SiO2 over Si3N4 can be achieved using ALE, but is subject to a transient period of reduced selectivity. Limitations of ALE due to realistic reactor conditions were found to limit these benefits in some cases.

Additional Information

Sponsor(s): Professor Mark Kushner

Open to: Public