#Build: Synplify Pro E-2010.09A-1, Build 006R, Oct  6 2010
#install: C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1
#OS: Windows XP 5.1
#Hostname: EECS373-07

#Implementation: synthesis

#Tue Sep 27 22:24:25 2011

$ Start of Compile
#Tue Sep 27 22:24:25 2011

Synopsys Verilog Compiler, version comp520rcp1, Build 028R, built Sep 23 2010
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\proasic\smartfusion.v"
@I::"C:\Actel\Libero_v9.1\Synopsys\synplify_E201009A-1\lib\vlog\hypermods.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\SmartFusionMSS\MSS\2.5.106\mss_comps.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\MSS_CCC_0\lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\mss_tshell.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_mss\lab4_mss.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v"
@I::"C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_top\lab4_top.v"
Verilog syntax check successful!
File C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED.v changed - recompiling
File C:\Documents and Settings\373a\Desktop\lab4fpga\hdl\ReadSW_WriteLED_wrp.v changed - recompiling
File C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v changed - recompiling
File C:\Documents and Settings\373a\Desktop\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v changed - recompiling
File C:\Documents and Settings\373a\Desktop\lab4fpga\component\work\lab4_top\lab4_top.v changed - recompiling
Selecting top level module lab4_top
@W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O

@N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3

	APB_DWIDTH=6'b100000
	RANGESIZE=21'b000000000000100000000
	IADDR_ENABLE=1'b0
	APBSLOT0ENABLE=1'b1
	APBSLOT1ENABLE=1'b0
	APBSLOT2ENABLE=1'b0
	APBSLOT3ENABLE=1'b0
	APBSLOT4ENABLE=1'b0
	APBSLOT5ENABLE=1'b0
	APBSLOT6ENABLE=1'b0
	APBSLOT7ENABLE=1'b0
	APBSLOT8ENABLE=1'b0
	APBSLOT9ENABLE=1'b0
	APBSLOT10ENABLE=1'b0
	APBSLOT11ENABLE=1'b0
	APBSLOT12ENABLE=1'b0
	APBSLOT13ENABLE=1'b0
	APBSLOT14ENABLE=1'b0
	APBSLOT15ENABLE=1'b0
	CAPB3O1I=32'b00000000000000000000000000001000
	CAPB3I1I=32'b00000000000000000000000000001000
	CAPB3l1I=8'b00001100
	CAPB3OOl=8'b00001000
	CAPB3IOl=8'b00000100
	CAPB3lOl=8'b00000000
	CAPB3OIl=8'b00000100
	CAPB3IIl=8'b00000000
	CAPB3lIl=8'b00000000
	CAPB3Oll=16'b0000000000000001
	CAPB3Ill=16'b0000000000000000
	CAPB3lll=16'b0000000000000000
	CAPB3O0l=16'b0000000000000000
	CAPB3I0l=16'b0000000000000000
	CAPB3l0l=16'b0000000000000000
	CAPB3O1l=16'b0000000000000000
	CAPB3I1l=16'b0000000000000000
	CAPB3l1l=16'b0000000000000000
	CAPB3OO0=16'b0000000000000000
	CAPB3IO0=16'b0000000000000000
	CAPB3lO0=16'b0000000000000000
	CAPB3OI0=16'b0000000000000000
	CAPB3II0=16'b0000000000000000
	CAPB3lI0=16'b0000000000000000
	CAPB3Ol0=16'b0000000000000000
   Generated name = CoreAPB3_Z1

@N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

@N:CG364 : ReadSW_WriteLED.v(52) | Synthesizing module Decoder3to8

@N:CG364 : ReadSW_WriteLED.v(3) | Synthesizing module ReadSW_WriteLED

@N:CG364 : ReadSW_WriteLED_wrp.v(3) | Synthesizing module ReadSW_WriteLED_wrp

@W:CS149 : ReadSW_WriteLED_wrp.v(39) | Port width mismatch for port bus_addr.  Formal has width 8, Actual 9
@N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

@N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

@N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC

@N:CG364 : smartfusion.v(1133) | Synthesizing module GND

@N:CG364 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module lab4_mss_tmp_MSS_CCC_0_MSS_CCC

@N:CG364 : mss_tshell.v(1) | Synthesizing module MSS_APB

@N:CG364 : lab4_mss.v(5) | Synthesizing module lab4_mss

@N:CG364 : lab4_top.v(5) | Synthesizing module lab4_top

@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(48) | Input MAINXIN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
@W:CL247 : ReadSW_WriteLED_wrp.v(19) | Input port bit 8 of PADDR[8:0] is unused

@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[3] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[4] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[5] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[6] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[7] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[8] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[9] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[10] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[11] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[12] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[13] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[14] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[15] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[16] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[17] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[18] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[19] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[20] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[21] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[22] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[23] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[24] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[25] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[26] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[27] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[28] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[29] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[30] is always 0, optimizing ...
@W:CL189 : ReadSW_WriteLED.v(25) | Register bit bus_read_data[31] is always 0, optimizing ...
@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 31 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 30 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 29 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 28 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 27 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 26 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 25 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 24 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 23 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 22 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 21 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 20 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 19 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 18 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 17 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 16 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 15 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 14 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 13 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 12 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 11 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 10 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 9 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 8 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 7 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 6 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 5 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 4 of bus_read_data[31:0] 

@W:CL260 : ReadSW_WriteLED.v(25) | Pruning Register bit 3 of bus_read_data[31:0] 

@W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 7 to 4 of bus_addr[7:0] are unused

@W:CL246 : ReadSW_WriteLED.v(14) | Input port bits 1 to 0 of bus_addr[7:0] are unused

@W:CL246 : ReadSW_WriteLED.v(16) | Input port bits 31 to 3 of bus_write_data[31:0] are unused

@W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused

@W:CL159 : coreapb3.v(208) | Input PRESETN is unused
@W:CL159 : coreapb3.v(210) | Input PCLK is unused
@W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused
@W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused
@W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused
@W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused
@W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused
@W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused
@W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused
@W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused
@W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused
@W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused
@W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused
@W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused
@W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused
@W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused
@W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused
@W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused
@W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused
@W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused
@W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused
@W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused
@W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused
@W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused
@W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused
@W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused
@W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused
@W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused
@W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused
@W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused
@W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused
@W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused
@W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused
@W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused
@W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused
@W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused
@W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused
@W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused
@W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused
@W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused
@W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused
@W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused
@W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused
@W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused
@W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused
@W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused
@W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 27 22:24:26 2011

###########################################################]

Synopsys Actel Technology Mapper, Version mapact, Build 023R, Built Sep 29 2010 09:29:00 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved Product Version E-2010.09A-1 @N:MF249 : | Running in 32-bit mode. @N:MF258 : | Gated clock conversion disabled @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) @W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) Available hyper_sources - for debug and ip models None Found @W: : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(81) | Net lab4_mss_0.MSS_ADLIB_INST_FCLK appears to be a clock source which was not identfied. Assuming default frequency. @W: : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(81) | Net ReadSW_WriteLED_wrp_0/PCLK appears to be a clock source which was not identfied. Assuming default frequency. Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB) Writing Analyst data base C:\Documents and Settings\373a\Desktop\lab4fpga\synthesis\lab4_top.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB) Writing EDIF Netlist and constraint files E-2010.09A-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB) @W:MT420 : | Found inferred clock lab4_mss|MSS_ADLIB_INST_EMCCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:lab4_mss_0.MSS_ADLIB_INST_EMCCLK" @W:MT420 : | Found inferred clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:lab4_mss_0_FAB_CLK" @W:MT420 : | Found inferred clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock with period 10.00ns. A user-defined clock should be declared on object "n:lab4_mss_0.MSS_ADLIB_INST_FCLK" ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Sep 27 22:24:29 2011 # Top view: lab4_top Library name: smartfusion Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree ) Requested Frequency: 100.0 MHz Wire load mode: top Wire load model: smartfusion Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -19.661 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock 100.0 MHz 33.7 MHz 10.000 29.661 -19.661 inferred Inferred_clkgroup_1 lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock 100.0 MHz 205.4 MHz 10.000 4.868 5.132 inferred Inferred_clkgroup_2 ========================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | 10.000 -19.661 | No paths - | No paths - | No paths - lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock | 10.000 5.132 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPSEL lab4_mss_0_MSS_MASTER_APB_PSELx 27.490 -19.661 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[9] lab4_mss_0_MSS_MASTER_APB_PADDR_\[9\] 2.679 3.355 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[8] lab4_mss_0_MSS_MASTER_APB_PADDR_\[8\] 2.679 3.494 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[11] lab4_mss_0_MSS_MASTER_APB_PADDR_\[11\] 2.679 3.494 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPADDR[10] lab4_mss_0_MSS_MASTER_APB_PADDR_\[10\] 2.679 3.633 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[0] PRDATA_0 10.000 -19.661 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[1] PRDATA_1 10.000 -19.661 lab4_mss_0.MSS_ADLIB_INST lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock MSS_APB MSSPRDATA[2] PRDATA_2_m1_0_a2 10.000 -19.661 ========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 29.661 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -19.661 Number of logic level(s): 1 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPSEL Ending point: lab4_mss_0.MSS_ADLIB_INST / MSSPRDATA[0] The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 27.490 27.490 - lab4_mss_0_MSS_MASTER_APB_PSELx Net - - 1.184 - 4 CoreAPB3_0.CAPB3llOI.PRDATA_0 NOR3C C In - 28.674 - CoreAPB3_0.CAPB3llOI.PRDATA_0 NOR3C Y Out 0.666 29.339 - PRDATA_0 Net - - 0.322 - 1 lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[0] In - 29.661 - ========================================================================================================== Total path delay (propagation time + setup) of 29.661 is 28.156(94.9%) logic and 1.505(5.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 29.661 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -19.661 Number of logic level(s): 1 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPSEL Ending point: lab4_mss_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 27.490 27.490 - lab4_mss_0_MSS_MASTER_APB_PSELx Net - - 1.184 - 4 CoreAPB3_0.CAPB3llOI.PRDATA_2_m1_0_a2 NOR3C C In - 28.674 - CoreAPB3_0.CAPB3llOI.PRDATA_2_m1_0_a2 NOR3C Y Out 0.666 29.339 - PRDATA_2_m1_0_a2 Net - - 0.322 - 1 lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 29.661 - ================================================================================================================ Total path delay (propagation time + setup) of 29.661 is 28.156(94.9%) logic and 1.505(5.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 29.661 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -19.661 Number of logic level(s): 1 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPSEL Ending point: lab4_mss_0.MSS_ADLIB_INST / MSSPRDATA[1] The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPSEL Out 27.490 27.490 - lab4_mss_0_MSS_MASTER_APB_PSELx Net - - 1.184 - 4 CoreAPB3_0.CAPB3llOI.PRDATA_1 NOR3C C In - 28.674 - CoreAPB3_0.CAPB3llOI.PRDATA_1 NOR3C Y Out 0.666 29.339 - PRDATA_1 Net - - 0.322 - 1 lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[1] In - 29.661 - ========================================================================================================== Total path delay (propagation time + setup) of 29.661 is 28.156(94.9%) logic and 1.505(5.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 6.645 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.355 Number of logic level(s): 3 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPADDR[9] Ending point: lab4_mss_0.MSS_ADLIB_INST / MSSPRDATA[0] The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPADDR[9] Out 2.679 2.679 - lab4_mss_0_MSS_MASTER_APB_PADDR_\[9\] Net - - 0.322 - 1 CoreAPB3_0.CAPB3O11_2_0[0] OR2 B In - 3.000 - CoreAPB3_0.CAPB3O11_2_0[0] OR2 Y Out 0.646 3.647 - CAPB3O11_2_0[0] Net - - 0.322 - 1 CoreAPB3_0.CAPB3O11_2[0] NOR2 B In - 3.968 - CoreAPB3_0.CAPB3O11_2[0] NOR2 Y Out 0.646 4.615 - CAPB3O11_2[0] Net - - 1.184 - 4 CoreAPB3_0.CAPB3llOI.PRDATA_0 NOR3C A In - 5.798 - CoreAPB3_0.CAPB3llOI.PRDATA_0 NOR3C Y Out 0.525 6.323 - PRDATA_0 Net - - 0.322 - 1 lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[0] In - 6.645 - =============================================================================================================== Total path delay (propagation time + setup) of 6.645 is 4.497(67.7%) logic and 2.148(32.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 6.645 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.355 Number of logic level(s): 3 Starting point: lab4_mss_0.MSS_ADLIB_INST / MSSPADDR[9] Ending point: lab4_mss_0.MSS_ADLIB_INST / MSSPRDATA[2] The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|MSS_ADLIB_INST_FCLK_inferred_clock [rising] on pin FCLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPADDR[9] Out 2.679 2.679 - lab4_mss_0_MSS_MASTER_APB_PADDR_\[9\] Net - - 0.322 - 1 CoreAPB3_0.CAPB3O11_2_0[0] OR2 B In - 3.000 - CoreAPB3_0.CAPB3O11_2_0[0] OR2 Y Out 0.646 3.647 - CAPB3O11_2_0[0] Net - - 0.322 - 1 CoreAPB3_0.CAPB3O11_2[0] NOR2 B In - 3.968 - CoreAPB3_0.CAPB3O11_2[0] NOR2 Y Out 0.646 4.615 - CAPB3O11_2[0] Net - - 1.184 - 4 CoreAPB3_0.CAPB3llOI.PRDATA_2_m1_0_a2 NOR3C A In - 5.798 - CoreAPB3_0.CAPB3llOI.PRDATA_2_m1_0_a2 NOR3C Y Out 0.525 6.323 - PRDATA_2_m1_0_a2 Net - - 0.322 - 1 lab4_mss_0.MSS_ADLIB_INST MSS_APB MSSPRDATA[2] In - 6.645 - =============================================================================================================== Total path delay (propagation time + setup) of 6.645 is 4.497(67.7%) logic and 2.148(32.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 Q led_reg[0] 0.737 5.132 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[1] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 Q led_reg[1] 0.737 5.132 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[2] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 Q led_reg[2] 0.737 5.132 ============================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 D led_reg_RNO[0] 9.427 5.132 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[1] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 D led_reg_RNO[1] 9.427 5.132 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[2] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1 D led_reg_RNO[2] 9.427 5.132 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.bus_read_data_1[2] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D bus_read_data_7[2] 9.427 6.032 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.bus_read_data_1[0] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D bus_read_data_7[0] 9.427 6.088 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.bus_read_data_1[1] lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock DFN1E0 D bus_read_data_7[1] 9.427 6.088 ================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.573 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.427 - Propagation time: 4.295 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 5.132 Number of logic level(s): 2 Starting point: ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] / Q Ending point: ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] / D The start point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK The end point is clocked by lab4_mss_tmp_MSS_CCC_0_MSS_CCC|lab4_mss_0_FAB_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------ ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] DFN1 Q Out 0.737 0.737 - led_reg[0] Net - - 1.708 - 10 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg_RNO_0[0] MX2 A In - 2.445 - ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg_RNO_0[0] MX2 Y Out 0.579 3.024 - N_12 Net - - 0.322 - 1 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg_RNO[0] NOR2B B In - 3.346 - ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg_RNO[0] NOR2B Y Out 0.627 3.973 - led_reg_RNO[0] Net - - 0.322 - 1 ReadSW_WriteLED_wrp_0.ReadSW_WriteLED_0.led_reg[0] DFN1 D In - 4.295 - ======================================================================================================================== Total path delay (propagation time + setup) of 4.868 is 2.516(51.7%) logic and 2.351(48.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] -------------------------------------------------------------------------------- Target Part: A2F200M3F_FBGA256_Std Report for cell lab4_top.verilog Core Cell usage: cell count area count*area GND 8 0.0 0.0 MSS_CCC 1 0.0 0.0 MX2 5 1.0 5.0 NOR2 1 1.0 1.0 NOR2B 5 1.0 5.0 NOR3A 1 1.0 1.0 NOR3C 4 1.0 4.0 OA1 1 1.0 1.0 OR2 2 1.0 2.0 OR3 1 1.0 1.0 OR3A 3 1.0 3.0 OR3B 4 1.0 4.0 OR3C 1 1.0 1.0 RCOSC 1 0.0 0.0 VCC 8 0.0 0.0 DFN1 3 1.0 3.0 DFN1E0 3 1.0 3.0 MSS_APB 1 0.0 0.0 ----- ---------- TOTAL 53 34.0 IO Cell usage: cell count INBUF 2 INBUF_MSS 1 OUTBUF 8 ----- TOTAL 11 Core Cells : 34 of 4608 (1%) IO Cells : 11 RAM/ROM Usage Summary Block Rams : 0 of 8 (0%) Mapper successful! Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Tue Sep 27 22:24:29 2011 ###########################################################]