The purpose of the online quizzes is to ensure that you have
read and understood the papers in advance of class.
The quiz questions are not intended to be difficult or tricky;
the answers to the questions should be known or easily found
by anyone who has read the paper. However, the questions are
designed so that you cannot easily find the answers within five
minutes if you have not read the papers in advance. Hence
read the papers before attempting the quizzes.
| Unit 1: Parallel Computing Models |
| L1: Introduction |
| M. D. Hill, S. Adve, L. Ceze, M. J. Irwin, D. Kaeli, M. Martonosi, J. Torrellas, T. F. Wenisch, D. Wood, K. Yelick - 21st Century Computer Architecture, CCC Whitepaper, 2012 |
| David Wood and Mark Hill, Cost-Effective Parallel Computing, IEEE Computer, 1995 |
| L2: Message Passing & Shared Memory |
| L3: Shared-Memory and Synchronization |
| Michael Scott, Shared-Memory Synchronization Synthesis Lectures on Computer Architecture (Ch. 1, 4.0-4.3.3, 5.0-5.2.5 |
| Using Message Passing to Transfer Data Between Threads - The Rust Programming Language |
| L4: Synchronization |
| L5: Transactional Memory |
| L6: Data-level Parallelism |
| Michael Scott, Shared-Memory Synchronization Synthesis Lectures on Computer Architecture (Ch. 9.0-9.2.3 |
| Unit 2: Coherence and Consistency |
| L7: Snooping Cache Coherence |
| Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood, A Primer on Memory Consistency and Cache Coherence, Second Edition (Ch. 6 & 7) |
| L8 Bus-Based SMPs |
| L9 Directory-based Coherence |
| Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood, A Primer on Memory Consistency and Cache Coherence, Second Edition (Ch. 8) |
| L10 Memory Consistency I |
| Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood, A Primer on Memory Consistency and Cache Coherence, Second Edition (Ch. 3 & 4) |
| A Safety-First Approach to Memory Models. Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd Millstein, Madanlal Musuvathi |
| L11 End-to-End SC |
| L12 Weaker Consistency Models |
| Unit 3: Accelerators |
| L14: GPUs |
| Tor M. Aamodt, Wilson Wai Lun Fung, Timothy G. Rogers, General-Purpose Graphics Processor Architectures (Ch. 3.1-3.3, 4.1-4.3) |
| L15: GPU Optimizations |
| L16: GPU Optimizations II |
| L17: Hardware Multi-threading |
| L18: Accelerators Intro |
| L19: Genomics Accelerators |
| Unit 4: Interconnects |
| L21: Interconnect Intro |
| L23: Interconnects: Routing |
| On-Chip Networks, Second Edition, Natalie Enright Jerger, Tushar Krishna, Li-Shiuan Peh |
