Simple Design Flow

• Behavioral Verilog
• Behavioral Verification (simulation, formal verification, or both)
• Synthesis in Synopsys
• Design for Testability
• Structural Verification (re-run same tests as before to make sure synthesis was correct)
• Timing Verification  - resynthesize if problems
• Floorplan
• Place & Route - refloorplan if problems
• Parasitic Extraction
• Timing Verification (with extracted SDF) - replace, reroute, refloorplan or resythesize if problems
• LVS/DRC/ERC