EECS 427 - VLSI Design I : Fall 2007

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Handouts

• Tutorial 1 Full-Custom Cadence flow tutorial of an inverter.


• Design Rules The design rules we will be using for TSMC 0.25 (A slightly modified version of the MOSIS DEEP rules) Most of the material was taken from MOSIS but stripped of extraneous information and modified where needed.


• Bus naming in cadence


• Bus tapping cadence


• Floorplanning in 3 layers of metal


• 427 Project ISA and baseline architecture


• Logical Effort Sample questions


• Tutorial 2 Custom Router tutorial